Graduate Intern TechnicalBookmark This
DescriptionIn this position, you will be part of a team implementing integrated graphics blocks on leading edge process technology. The team is responsible for all structural design optimization flows ranging from Floorplanning, Synthesis through GDS and parallel verification flows such as Static Timing Analysis, Formal Verification, Layout Verification etc. Internships are 6 to 9 months in length.
The ideal candidate will start off as a Junior Execution or Process Owner who will work with Senior Execution/ Process Owners with development/ implementation and execution of a range of flows on a given design block for CGDG gen graphics projects. The responsibilities may also include coming up with new methodologies/ implementing them and validating them to tackle new challenges presented by the new processes. The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle. Finally, the candidate would give feedback of key learnings into the next chip cycle. Good interpersonal/communication skills are necessary due to the nature of work and the size of the team.
- Must be currently enrolled fulltime in a MS or PhD program in Electrical Engineering or Computer Engineering
General Knowledge in one or more of ASIC style design flows - floorplanning, synthesis, place route, layout verification, static timing analysis, formal/ layout verification - flows/processes is desired. Hands-on experience with any of the industry tools in these areas will be an added plus.
Knowledge and Experience with Unix/ Linux, Perl and TCL are also desired in order to implement useable, flexible cshell/ perl/ tcl programs that automate tool/flow methodologies.