Graduate Intern Technical

Bookmark This
Intel Corporation
Folsom, CA
Application Deadline: No Deadline
Position: Full-time, Unpaid

Login or Sign Up to apply.



In this position, you will be part of a team implementing integrated graphics blocks on leading edge process technology. The team is responsible for all structural design optimization flows ranging from Floorplanning, Synthesis through GDS and parallel verification flows such as Static Timing Analysis, Formal Verification, Layout Verification etc. The ideal candidate will start off as a Junior Execution or Process Owner who will work with Senior Execution/ Process Owners with development/ implementation and execution of a range of flows on a given design block for CGDG gen graphics projects. The responsibilities may also include coming up with new methodologies/ implementing them and validating them to tackle new challenges presented by the new processes. The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle. Finally, the candidate would give feedback of key learnings into the next chip cycle. Good interpersonal/communication skills are necessary due to the nature of work and the size of the team.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:
- Must be pursuing a MS or PhDdegree in Computer Science, Computer Engineering, and/or Electrical Engineering

Engineering or equivalent. Relevant coursework/experience should be in the following areas:
ASIC Design

Preferred Requirements:

General Knowledge in one or more of ASIC style design flows - floorplanning, synthesis, place route, layout verification, static timing analysis, formal/ layout verification - flows/processes is desired.
Hands-on experience with any of the industry tools in these areas will be an added plus.

Knowledge and Experience with Unix/ Linux, Perl and TCL are also desired in order to implement useable, flexible cshell/ perl/ tcl programs that automate tool/flow methodologies.

How To Apply

Login or Sign Up to apply.