Logic Design Intern

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Intel Corporation
Folsom, CA
Application Deadline: No Deadline
Position: Full-time, Unpaid

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In this position, you will be working as Intern with Intel IPG design team based in Folsom working on leading edge IP designs.

The team is looking for Logic Design interns with strong RTL Design and Validation knowledge. Your responsibilities will include but not be limited to:
- Responsible for the logic implementation of design block(s) using RTL coding techniques
- Working with the Physical Design (Layout) team on Synthesis, Formal Verification and Timing Convergence.

You must be enrolled in Master's degree in Electrical Engineering, Computer Engineering or a related discipline. You must be able to commit to Internship position for 5 months or more. Additional qualifications include:
- A good academic understanding of Computer Architecture, RTL level Digital IC Design using System Verilog* and/or Verilog*
- Experience with languages such as Verilog, System Verilog*, Perl, Sell scripting
- Knowledge of industry standard ASIC development tools and methodologies
- Experience with logic simulation tools such as VCS*
- Working knowledge of synthesis and Static Timing Analysis (STA) with Design Compiler and Primetime*
- Ability to work well in a diverse team environment
- Excellent communication, interpersonal and problem solving skills
- Motivated, self-directed and able to work effectively both independently and in a team
- Good planning skills

How To Apply

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