Logic Technology Development Reliability Graduate Intern

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Intel Corporation
Hillsboro, OR
Application Deadline: No Deadline
Position: Full-time, Unpaid

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Description

Job Description: Responsibilities may consist of measurement data acquisition and analysis of electron devices, building device level models, or other types of data analysis related to transistor, interconnect, defect reliability, Si-package interaction, or soft error rate development efforts. Intern will be responsible for data collection, analysis, model formulation, and communicating results based on a 3 month summer project.
Qualifications
Qualifications:
You must possess the minimum qualifications to be considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates. Experience can be obtained through a combination of prior education, current Ph.D. course work, projects, research and any relevant prior job/internships.

Minimum Qualifications:
This is an entry level position for a college graduate student working towards a Ph.D. degree in Electrical Engineering, Material Science, Physics or related discipline.

Preferred Qualifications:
-Experience in experimental design, execution, and interpretation.
-Experience with electron device fabrication and characterization.
-Experience with electrical measurement equipment in characterizing electron devices (e.g. HP4155, oscilloscope, etc.)
-Experience with a range of analytical techniques such as SIMS, EEL, EDX, XPS, Auger, acoustic profiling, FTIR, AFM, etc.
-Experience with various lab imaging techniques (SEM, FIB, TEM, etc.)
-Knowledge in one or more of the following areas electron device fabrication, semiconductor device physics, CMOS transistor level circuit design, interconnect reliability, soft error rate and circuit simulations, PCB fabrication principles, surface mount assembly, board test methods, solder and laminate material behavior under mechanical or thermo-mechanical conditions.
-Knowledge of semiconductor wafer fabrication process and process integration challenges.
-Knowledge of silicon and packaging assembly integration, or PCB technology operations
-Understanding of reliability failure statistics, physics, or failure mechanisms.
-Experience programming with formal language (C,C++, C#, etc.) and scripting language (AWK, PERL, Python, SQL, TCL, VBScript, etc.)
-Experience with sequel or SQL data extraction.
-Experience with statistical analysis packages (e.g. SAS, JMP, Minitab, R, etc.)
-Prior Intel Intern or Scholarship recipient

How To Apply

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