SCDC Engineering Intern (BS Level)Bookmark This
Santa Clara, CA
Job Description: Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.Candidate will be a member of Backend (Physical Implementation) Team within Server CPU Design Group (within Intel Architecture Group). Candidate will be involved in design, verification and layout of special circuits such as high-speed I/O buffer, SRAM and PLL cells for use in integrated circuit design. Candidate will be expected to work closely with a team of circuit design engineers and mask design technicians to develop the layout of special circuits and verify their electrical characteristics. Design tasks include specification, planning, schematic generation, circuit simulation, timing analysis, design reviews, layout supervision and coordination of final application of circuits in chip level layout. The position requires an in-depth understanding of CMOS technology , logic circuits, CMOS layout, device physics, design CAD tools, circuit reliability, and signal integrity.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
- Must be pursuing a BS degree inElectrical Engineering, Computer Engineering, Computer Scienceor or other science/engineering related field - Must have the unrestricted right to work in the US without requiring sponsorship - Minimum of 3 months experience with software/programming languages (i.e. C, C++, C#, Visural.NET/Bacis, Perl, Java, etc.) Preferred Qualifications: - Minimum of 3 months experience withCMOS technology and layout - Minimum of 3 months experience with logic circuits - Minimum of 3 months experience with device physics - Minimum of 3 months experience with design CAD tools, circuit reliability - Minimum of 3 months experience with signal integrity