Address: 830 stewart dr suite 282
Location: Sunnyvale, CA
Application Deadline: Available Year-round
Position: Part-time, Paid
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Description
Ausdia is looking for a exceptional, capable intern with experience in VLSI design and SOC design concepts (RTL/verilog, synthesis, place/route, timing analysis). Academic and personal experience will be accepted.
We are looking to build a solid, long-term relationship with the right candidate that can eventuate in a full-time position and the end of your studies. You should be prepared to work in a face-paced, small-company startup environment.
Responsibilities
- documentation and test of complex software applications
- research, algorithm design and implementation of new application ideas
- translation of customer requirements into algorithm and applications
- other duties as appropriate in small company environment
Requirements
Excellent analytical and math skills, and solid understanding of VLSI design and computer science, including algorithm design and implementation. We are looking for students majoring in computer science and electrical engineering, preferrable towards Masters degree level. We are also looking for candidates who show aptitude and interest in non-core-academic areas.
